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the a4928 is an n-channel power mosfet driver capable of controlling mosfets connected in a half-bridge arrangement and is specifically designed for automotive applications with high-power inductive loads, such as brush dc motors solenoids and actuators. the a4928 is intended for automotive systems that must meet asil requirements. in common with other allegro a 2 sil ? products, this device incorporates features to complement proper system design, allowing users to achieve the required asil level. a unique charge pump regulator provides full gate drive for battery voltages down to 5.5 v for most applications. a bootstrap capacitor is used to provide the above-battery supply voltage required for n-channel mosfets. the half bridge can be controlled by independent logic-level inputs or through the spi-compatible serial interface. the external power mosfets are protected from shoot-through by a programmable dead time. integrated diagnostics provide indication of multiple internal faults, system faults, and power bridge faults, and can be configured to protect the power mosfets under most short- circuit conditions. in addition to providing full access to the bridge control, the serial interface is also used to alter programmable settings such as dead time, v ds threshold, and fault blank time. detailed diagnostic information can be read through the serial interface. the a4928 is supplied in a 24-lead etssop (suffix lp). this package is lead (pb) free, with 100% matte-tin leadframe plating (suffix Ct). a4928-ds, rev. 1 mco-0000332 ? half-bridge mosfet driver ? bootstrap gate drive for n-channel mosfet bridge ? cross-conduction protection with adjustable dead time ? charge pump regulator for low supply voltage operation ? 5.5 to 50 v supply voltage operating range ? 5 v cmos logic i/o ? spi-compatible serial interface ? bridge control by direct logic inputs or serial interface ? programmable gate drive ? current sense amplifier ? programmable diagnostics ? automotive aec-q100 qualified ? a 2 sil? productdevice features for safety-critical systems automotive half-bridge mosfet driver package: figure 1 : typical application not to scale a4928 features and benefits description january 31, 2019 2 - 24-lead tssop with exposed pad (suffix lp) spi a4 928 gnd vbat ecu lo ad ? anti-lock braking systems (abs) ? hvac (blower fan) ? dc pumps (fuel, oil, water) ? solenoids and actuators ? similar industrial applications applications
2 absolute maximum ratings [1] characteristic symbol notes rating unit load supply voltage v bb C0.3 to 50 v regulator output v reg vreg C0.3 to 16 v charge pump capacitor terminal v cp1 cp1 C0.3 to 16 v charge pump capacitor terminal v cp2 cp2 v cp1 C 0.3 to v reg + 0.3 v battery-compliant logic input terminals v ib hs, lsn, resetn, enable C0.3 to 50 v logic input terminals v i strn, sck, sdi C0.3 to 6 v logic output terminal v o sdo C0.3 to 6 v diagnostics output v diag diag C0.3 to 50 v sense amplifier inputs v csi csp, csm C4 to 6.5 v sense amplifier output v cso cso, oos C0.3 to 6 v bridge drain monitor terminal v brg vbrg C5 to 55 v bootstrap supply terminal v c c C0.3 to v reg + 50 v high-side gate drive output terminal v gh gh v c C 16 to v c + 0.3 v gh (transient) C18 to v c + 0.3 v high-side source (load) terminal v s s v c C 16 to v c + 0.3 v s (transient) C18 to v c + 0.3 v low-side gate drive output terminal v gl gl v reg C 16 to 18 v gl (transient) C8 to 18 v bridge low-side source terminal v lss lss v reg C 16 to 18 v lss (transient) C8 to 18 v ambient operating temperature range t a limited by power dissipation C40 to 150 c maximum continuous junction temperature t j(max) 165 c transient junction temperature t jt overtemperature event not exceeding 10 seconds, lifetime duration not exceeding 10 hours, guaranteed by design characterization. 180 c storage temperature range t stg C55 to 150 c [1] with respect to gnd. ratings apply when no other circuit operating constraints are present. selection guide part number packing package A4928KLPTR-T 4000 pieces per reel 7.8 mm 4.4 mm, 1.2 mm max height 24-lead tssop with exposed thermal pad thermal characteristics : may require derating at maximum conditions characteristic symbol test conditions [2] value unit package thermal resistance r ja 4-layer pcb based on jedec standard 28 c/w 2-layer pcb with 3.8 in. 2 copper each side 38 c/w r jp 2 c/w [2] additional thermal information available on the allegro website. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
3 table of contents features and benefits ....................................................... 1 description ........................................................................ 1 package ............................................................................ 1 typical application ............................................................ 1 selection guide ................................................................. 2 absolute maximum ratings .............................................. 2 thermal characteristics .................................................... 2 pinout diagram and terminal list table ........................... 4 functional block diagram ................................................. 5 electrical characteristics ................................................... 6 supply and reference ....................................................... 6 gate output drive ............................................................. 7 logic inputs and outputs ................................................... 8 logic i/o C dynamic parameters ......................................... 8 current sense amplifier ..................................................... 9 diagnostics and protection ............................................... 10 timing diagrams .............................................................. 11 logic truth tables ........................................................... 13 functional description .................................................... 14 input and output terminal functions ................................. 14 power supplies ............................................................... 15 pump regulator .............................................................. 15 gate drives .................................................................... 15 bootstrap supply ............................................................ 15 bootstrap charge management ........................................ 15 top-off charge pump ...................................................... 16 high-side gate drive ....................................................... 16 low-side gate drive ....................................................... 16 gate drive passive pull-down .......................................... 17 dead time ..................................................................... 17 gate drive control .......................................................... 17 logic control inputs ........................................................ 18 output disable ................................................................ 18 sleep mode .................................................................... 19 current sense amplifier ................................................... 19 diagnostic monitors ......................................................... 19 status and diagnostic registers ....................................... 20 chip-level protection ...................................................... 20 operational monitors ....................................................... 21 power bridge and load faults .......................................... 21 fault action .................................................................... 24 fault masks ................................................................... 25 serial interface ................................................................ 26 configuration registers ................................................... 28 diagnostic registers ....................................................... 28 control register .............................................................. 28 status register ............................................................... 29 serial register reference ............................................... 30 application information ................................................... 36 dead-time selection ....................................................... 36 bootstrap capacitor selection .......................................... 36 bootstrap charging ......................................................... 36 vreg capacitor selection ............................................... 37 current sense amplifier configuration ............................... 37 current sense amplifier output signals ............................. 37 input/output structures ................................................... 38 layout recommendations .............................................. 39 package outline drawing ............................................... 40 automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
4 terminal list table name number function c 19 bootstrap capacitor cp1 22 pump capacitor ccp connection cp2 21 pump capacitor ccp connection csm 13 current sense amplifier (C) input cso 12 current sense amplifier output csp 14 current sense amplifier (+) input diag 2 diagnostic output enable 3 gate drive output control input gh 17 high-side gate drive output gl 16 low-side gate drive output gnd 1 power ground hs 5 hs control input lsn 6 ls control input lss 15 low-side source oos 11 sense amplifier offset output resetn 4 standby mode control input s 18 load connection sck 8 serial clock input sdi 7 serial data input sdo 9 serial data output strn 10 serial strobe (chip select) input vbb 23 main power supply vbrg 24 high-side drain voltage sense vreg 20 regulated gate drive supply pad C thermal pad; connect to gnd 24-lead etssop (sufx lp) pinout diagram pinout diagram and terminal list table 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 vbrg vbb cp1 cp2 vreg c s gh gl lss csp cms gnd diag enable resetn hs lsn sdi sck sdo strn oos cso pad automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
5 figure 2: functional block diagram c ont rol log ic c cp cp1 cp2 vbb vbat vreg c reg logic supply regulator c harge pump r egu lator c ha rge pump b oo tstrap m on itor vds m on itor vds m on itor ls drive hs drive timers s er ial interface dac dac di agno stics & p ro tection v oos gnd pad strn hs lsn diag sck sdi r es etn en ab le sdo oos lss gl gh s vb rg c csp csm cso log ic i/o regulator automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
6 electrical characteristics: valid for t j = C40 to 150c, v bb = 5.5 to 50 v, unless otherwise specified characteristics symbol test conditions min. typ. max. unit supply and reference vbb functional operating range v bb operating; outputs active 5.5 C 50 v operating; outputs disabled 5 C 50 v no unsafe states 0 C 50 v vbb quiescent current i bbq resetn = high, v bb = 12 v, all gate drive outputs low C 8 20 ma i bbs 5(6(7q p9vohhsprgh9 bb < 35 v C C 20 a internal logic supply regulator voltage [3][4] v dl 3.1 3.3 3.5 v logic i/o regulator voltage [3][4] v io v bb > 6 v 4.8 5 5.2 v vreg output voltage, vrg = 0 v reg v bb > 7.5 v, i vreg = 0 to 30 ma 7.5 8 8.5 v 6 v < v bb 9, vreg = 0 to 13 ma 7.5 8 8.5 v 5.5 v < v bb 9, vreg < 8 ma 7.5 8 8.5 v vreg output voltage, vrg = 1 v reg v bb > 9 v, i vreg = 0 to 30 ma 9 11 11.7 v 7.5 v < v bb 9, vreg = 0 to 20 ma 9 11 11.7 v 6 v < v bb 9, vreg wrp 7.9 C C v 5.5 v < v bb 9, vreg < 8 ma 7.9 9.5 C v bootstrap diode forward voltage v fboot i d = 10 ma 0.4 0.7 1.0 v i d = 100 ma 1.2 1.9 2.5 v bootstrap diode current limit i dboot 250 500 750 ma top-off charge pump current limit i tocpm 50 100 C a high-side gate drive static load resistance r gsh 250 C C n system clock period t osc 42.5 50 57.5 ns continued on the next page automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
7 electrical characteristics (continued): valid for t j = C40 to 150c, v bb = 5.5 to 50 v, unless otherwise specified characteristics symbol test conditions min. typ. max. unit gate output drive turn-on time t r c load = 10 nf, 20% to 80% C 190 C ns turn-off time t f c load = 10 nf, 80% to 20% C 120 C ns pull-up peak source current i pupk C 400 C ma pull-up on resistance r ds(on)up t j = 25c, i gh = C150 ma [1] 4 6 10.5 t j = 150c, i gh = C150 ma [1] 9.5 12 19 pull-down peak sink current i pdpk C 800 C ma pull-down on resistance r ds(on)dn t j = 25c, i gl = 150 ma 1.5 2.4 3.1 t j = 150c, i gl = 150 ma 2.9 4 5.5 gh output voltage high v ghh v c C 0.2 C C v gh output voltage low v ghl C10 a < i gh < 10 a C C v s + 0.3 v gl output voltage high v glh v reg C 0.2 C C v gl output voltage low v gll C10 a < i gl < 10 a C C v lss + 0.3 v gh passive pull-down r ghpd v gh C v s < 0.3 v C 950 C n v gl C v lss < 0.3 v C 950 C n turn-off propagation delay t p(off) input change to unloaded gate output change, (figure 5) dt[9:0] = 0 60 90 140 ns input change to unloaded gate output change, (figure 5) dt[9:0] > 0 135 165 215 ns turn-on propagation delay t p(on) input change to unloaded gate output change, (figure 5) dt[9:0] = 0 50 80 130 ns input change to unloaded gate output change, (figure 5) dt[9:0] > 0 125 155 205 ns propagation delay matching (on-to-off) w oo dt[9:0] = 0 C 15 30 ns propagation delay matching (gh-to-gl) w hl same state change, dt[9:0] = 0 C C 20 ns dead time (turn-off to turn-on delay) t dead default power-up state ( figure 5) 40 51.15 62.35 s programmable range dt[9:0], nominal 0.1 C 51.15 s continued on the next page automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
8 electrical characteristics (continued): valid for t j = C40 to 150c, v bb = 5.5 to 50 v, unless otherwise specified characteristics symbol test conditions min. typ. max. unit logic input and outputs input low voltage v il C C 1.5 v input high voltage v ih all logic inputs 3.5 C C v input hysteresis v ihys resetn inputs 200 400 C mv all other logic inputs 250 550 C mv input pull-down hs, enable, resetn r pd 0 < v in < 5 v C 50 C n i pd 5 v < v in < 50 v C 100 C a input pull-down sdi, sck r pds 0 < v in < 5 v C 50 C n input pull-up current to vdl i pu strn C 100 C a input pull-up to vdl r pu lsn C 170 C n output low voltage sdo, diag v ol i ol = 1 ma C 0.1 0.4 v output high voltage sdo v ohs i os = C200 a [1] v io C 0.1 C C v i os = C1 ma [1] v io C 0.4 C C v output leakage sdo [1] i os 0 v < v os < v io , strn = 1 C1 C 1 a output current limit (diag) i oldlim 0 v < v od < 12 v, diag active C 10 17 ma 99 od < 50 v, diag active C C 2.5 ma output leakage [1] (diag) i od 0 v < v od < 12 v, diag inactive C1 C 1 a 99 od < 50 v, diag inactive C C 2.5 ma logic i/o C dynamic parameters reset pulse width t rst 0.5 C 4.5 s reset shutdown time t rsd 30 C C s input pulse filter time t pin hs, lsn C 35 C ns clock high time t sckh a in figure 4 50 C C ns clock low time t sckl b in figure 4 50 C C ns strobe lead time t stld c in figure 4 30 C C ns strobe lag time t stlg d in figure 4 30 C C ns strobe high time t strh e in figure 4 300 C C ns data out enable time t sdoe f in figure 4 C C 40 ns data out disable time t sdod g in figure 4 C C 30 ns data out valid time from clock falling t sdov h in figure 4 C C 40 ns data out hold time from clock falling t sdoh i in figure 4 5 C C ns data in set-up time to clock rising t sdis j in figure 4 15 C C ns data in hold time from clock rising t sdih k in figure 4 10 C C ns wake up from sleep t en C C 2 ms continued on the next page automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
9 electrical characteristics (continued): valid for t j = C40 to 150c, v bb = 5.5 to 50 v, unless otherwise specified characteristics symbol test conditions min. typ. max. unit current sense amplifier input offset voltage v ios C4 C +4 mv input offset voltage drift 9 ios C 4 C v/c input bias current [1] i bias 0 v < v csp < v dl , 0 v < v csm < v dl C16 C 31 a input offset current [1] i os v id = 0 v, v cm in range C10 C +10 a input common-mode range (dc) v cm v id = 0 v C1.8 C +2 v gain a v default power-up value C 35 C v/v programmable range, sag[2:0], nominal 10 C 50 v/v gain error e a v cm in range C5 2 +5 % output offset v oos default power-up value C 2.5 C v programmable range, sao[3:0], nominal 0 C 2.5 v output offset error e vo v cm in range, v oos > 0 v C10 2 +10 % small signal C3 db bandwidth at gain = 25 bw v in = 10 mv pp 500 C C khz output settling time (to within 40 mv) t set v cso = 1 v pp square wave gain = 25, c out = 200 pf C 1 1.8 s output dynamic range v csout C100 a < i cso < 100 a 0.3 C 4.8 v output voltage clamp v csc i cso = C2 ma 4.85 5.2 5.6 v output current sink [1] i cssink v id = 0 v, v cso = 1.5 v, gain = 25 0.275 C C ma output current sink (boosted) [1][5] i cssinkb v oos = 0 v, v id = C50 mv, v cso = 1.5 v, gain = 25 1 C C ma output current source [1] i cssource v id = 200 mv, v cso = 1.5 v gain = 25, offset = 0 v C C C1 ma vbb supply ripple rejection ratio psrr v id = 0 v, 100 khz, gain = 25 C 75 C db v csp = v csm = 0 v, dc, gain = 25 75 C C db dc common-mode rejection ratio cmrr v cm step from 0 to 200 mv gain = 25 55 C C db ac common-mode rejection ratio cmrr v cm = 200 mv pp , 100 khz, gain = 25 C 62 C db v cm = 200 mv pp , 1 mhz, gain = 25 C 43 C db v cm = 200 mv pp , 10 mhz, gain = 25 C 25 C db common mode recovery time (to within 100 mv) t cmrec v cm step from C4 v to +1 v gain = 25, c out = 200 pf C 1 C s output slew rate 10% to 90% sr v id step from 0 to 175 mv gain = 25, c out = 200 pf C 10 C v/s input overload recovery (to within 100 mv) t idrec v id step from 250 mv to 0 v gain = 25, c out = 200 pf C 1 C s continued on the next page automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
10 electrical characteristics (continued): valid for t j = C40 to 150c, v bb = 5.5 to 50 v, unless otherwise specified characteristics symbol test conditions min. typ. max. unit diagnostics and protection vreg undervoltage vrg = 0 v ron v reg rising 6.4 6.6 6.7 v v roff v reg falling 5.5 5.7 5.9 v vreg undervoltage vrg = 1 v ron v reg rising 7.6 7.95 8.2 v v roff v reg falling 6.9 7.15 7.4 v vreg overvoltage warning v rov v reg rising 15.5 15.9 16.5 v vreg overvoltage hysteresis v rovhys 1200 1500 C mv vbb overvoltage warning v bbov v bb rising 32 C 36 v vbb overvoltage hysteresis v bbovhys 1 C C v vbb por voltage v bbr v bb C 3.5 C v bootstrap undervoltage v bcuv v boot falling, v boot = v c C v s 56 C 64 %v reg bootstrap undervoltage hysteresis v bcuvhys C 13 C %v reg gate drive undervoltage warning hs v gshuv v gsh v boot C 1.25 v boot C 1 v boot C 0.8 v gate drive undervoltage warning ls v gsluv v gsl v reg C 1.25 v reg C 1 v reg C 0.8 v vbrg input voltage v brg when vds monitor is active 5.5 v bb 50 v vbrg input current i vbrg v dsth = default, v bb = 12 v 0 v < v brg < v bb C C 500 a i vbrgq sleep mode v bb < 35 v C C 5 a vds threshold C high side v dsth default power-up value 1.1 1.2 1.3 v programmable range vt[5:0], nominal 0 C 3.15 v programmable range vt[5:0] 99 brg < 7 v [6] 0 C 1.5 v high-side vds threshold offset [2] v dstho high-side on, v dsth 99 brg > 7 v C200 100 200 mv high-side on, v dsth < 1 v C150 50 150 mv vds threshold C low side v dstl default power-up value 1.1 1.2 1.3 v programmable range, v bb 9 [6] 0 C 3.15 v low-side vds threshold offset [2] v dstlo low-side on, v dstl 99 brg > 7 v C200 100 200 mv low-side on, v dstl < 1 v C150 50 150 mv vds and vgs qualify time t vdq default power-up value ( figure 6) 86.96 102.3 117.65 s programmable range tvd[9:0], nominal 0 C 102.3 s overcurrent voltage v oct default power-up value 2.7 3.0 3.3 v programmable range, oct[3:0], nominal 0.3 C 4.8 v overcurrent qualify time t ocq 6.75 7.5 8.25 s temperature warning threshold t jwh temperature increasing 125 135 145 c temperature warning hysteresis t jwhhys recovery = t jwh C t jwhhys C 15 C c overtemperature threshold t jf temperature increasing 170 175 180 c overtemperature hysteresis t jhys recovery = t jf C t jhys C 15 C c [1] for input and output current specifications, negative current is defined as coming out of (sourcing) the specified device terminal. [2] vds offset is the difference between the programmed threshold, v dsth or v dstl and the actual trip voltage. [3] vio, vdl derived from vbb for internal use only. not accessible on any device terminal. [4] verified by design and characterization. [5] if the amplifier output voltage (v cso ) is more positive than the value demanded by the applied differential input (v id ) and output offset (v oos ) conditions, then output current sink capability is boosted to enhance negative-going transient response. [6] maximum value of vds threshold that should be set in the configuration registers for correct operation when v brg is within the stated range. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
11 x x x x x c a b d e j k f i g d15 d14 d0 d 15? d 14? d0? strn sck sdi sdo h z z hs lsn gh gl t dead t dead t p(o ff) t p(o ff) t p(on) t p(o ff) t p(on) t p(o ff) sync hronou s rectification high - si de pwm low - si de pwm figure 3 : sense amplifer voltage defnitions figure 4 : serial interface timing (x = dont care, z = high impedance (tri-state)) figure 5 : gate drive timing C control inputs a4928 r s i ph v csp v cm = (v csp + v csm ) / 2 v id csp csm v csm a v gnd oos cso v csd v cso v oos a v set by sag[2:0] v oos set by sao[3:0] v cso = [(v csp + v csm ) a v ] + v oos automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
12 g x vd s f au lt bi t mosfet t urn on f au lt pr es ent mosfet on t ran si en t dist urban ce no f au lt pres ent mosfet on f au lt occ urs mosfet t urn on no f au lt pres ent t vdq t vdq mosfet t urn on no f au lt pres ent mosfet t urn on f au lt pr es ent mosfet on t ran si en t dist urban ce no f au lt pres ent mosfet on f au lt occ urs g x vd s f au lt bi t t vdq t vdq t vdq t vdq figure 6 a: vds fault monitor C blank mode timing (vdq = 1) figure 6 b: vds fault monitor C debounce mode timing (vdq = 0) automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
13 logic truth tables table 1 : control logic (control by logic inputs) hs lsn gh gl s 0 1 lo lo z 0 0 lo hi lo 1 1 hi lo hi 1 0 lo lo z hi = high-side fet active, lo = low-side fet active z = high impedance, both fets off all control register bits set to 0, resetn = 1, enable = 1 internal control signals (hi, lo) are derived by combining the logic states applied to the control input terminals (hs, ls) with the bit patterns held in the control register (hsr, lsr). normally the input terminals or the control register method is used for control with the other being held inactive (all termials or bits at logic 0). table 2 : control logic (control by serial register) hsr lsr gh gl s 0 0 lo lo z 0 1 lo hi lo 1 0 hi lo hi 1 1 lo lo z hi = high-side fet active, lo = low-side fet active z = high impedance, both fets off hs = 0, lsn = 1, resetn = 1, enable = 1 table 3 : control combination logic table C logic inputs and serial register terminal register internal terminal register internal hs hsr hi lsn lsr lo 0 0 0 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 1 1 1 1 1 1 enable hi lo gh gl s comment 1 0 0 l l z bridge disabled 1 0 1 l h lo bridge sinking 1 1 0 h l hi bridge sourcing 1 1 1 l l z bridge disabled 0 x x l l z bridge disabled x = dont care automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
14 functional description the a4928 is a half-bridge (h-bridge) mosfet driver (pre- driver) requiring a single unregulated supply of 5.5 to 50 v . it includes an integrated linear regulator to supply the internal logic. all logic inputs are ttl compatible and can be driven by 3.3 or 5 v logic. the two high-current gate drives are capable of driving a wide range of n-channel power mosfets, and are configured as a half-bridge driver with one high-side drive and one low-side drive. the a4928 provides all necessary circuits to ensure that the gate-source voltage of both high-side and low-side external fets are above 10 v , at supply voltages down to 7 v . for extreme battery voltage drop conditions, correct functional operation is guaranteed at supply voltages down to 5.5 v , but with a reduced gate drive voltage. gate drives can be controlled directly through the logic input ter - minals or through an spi-compatible serial interface. the sense of the logic inputs are arranged to allow the bridge to be driven by a single pwm input if required. the bridge can also be driven by direct logic inputs or by two pwm signals depending on the required complexity. the logic inputs are battery voltage compli - ant, meaning they can be shorted to ground or supply without damage, up to the maximum battery voltage of 50 v . bridge efficiency can be enhanced by using the synchronous rectification ability of the drives. when synchronous rectification is used, cross-conduction (shoot through) in the external bridge is avoided by an adjustable dead time. a hardwired logic lockout ensures that the high-side and the low-side cannot be permanently active at the same time. a low-power sleep mode allows the a4928, the power bridge, and the load to remain connected to a vehicle battery supply with - out the need for an additional supply switch. the a4928 includes a number of diagnostic features to provide indication and/or protection against undervoltage, overtempera - ture, and power bridge faults. a single diagnostic output provides basic fault indication and detailed diagnostic information is available through the serial interface. the serial interface also provides access to programmable dead time, fault blanking time and programmable vds threshold for short detection. the a4928 includes a low-side current sense amplifier with pro - grammable gain and offset. the amplifier is specifically designed for current sensing in the presence of high voltage and current transients. input and output terminal functions vbb: main power supply for internal regulators and charge pump. the main power supply should be connected to vbb through a reverse voltage protection circuit and should be decoupled with ceramic capacitors connected close to the supply and ground terminals. vbrg: sense input to the top of the external mosfet bridge. allows accurate measurement of the voltage at the drain of the high-side mosfet in the bridge. cp1, cp2: pump capacitor connection for charge pump. con- nect a minimum 220 nf, typically 470 nf, ceramic capacitor between cp1 and cp2. vreg: programmable regulated voltage, 8 or 11 v , used to sup - ply the low-side gate drivers and to provide current for the above supply charge pump. a sufficiently large storage capacitor must be connected to this terminal to provide the required transient charging current. gnd: analog, digital, and power ground. connect to supply groundCsee layout recommendations . c: high-side connection for the bootstrap capacitor and positive supply for the high-side gate driver. gh: high-side, gate-drive output for an external n-channel mosfet. s: source connection for high-side mosfet providing the nega - tive supply connections for the floating high-side driver. gl: low-side gate-drive output for an external n-channel mos - fet. lss: low-side return path for discharge of the capacitance on the low-side mosfet gate, connected to the source of the low- side external mosfet independently through a low-impedance track. hs: logic inputs with pull-down to control the high-side gate drive. battery voltage compliant terminal. lsn: logic input with pull-up to control the low-side gate drive. this is an active-low input. battery voltage compliant terminal. enable: logic input to enable the gate drive outputs. battery voltage compliant terminal. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
15 resetn: clears latched fault states that may have disabled the outputs when taken low for the reset pulse width, t rst . forces low-power shutdown (sleep) when held low for more than the reset shutdown time, t rsd . battery voltage compliant terminal. sdi: serial data logic input with pull-down. 16-bit serial word input msb first. sdo: serial data output. high impedance when strn is high. outputs bit 15 of the diagnostic register, the fault flag, as soon as strn goes low. sck: serial clock logic input with pull-down. data is latched in from sdi on the rising edge of sck. there must be 16 rising edges per write and sck must be held high when strn changes. strn: serial data strobe and serial access enable logic input with pull-up. when strn is high, any activity on sck or sdi is ignored and sdo is high impedance, allowing multiple sdi slaves to have common sdi, sck, and sdo connections. csp, csm: current sense amplifier inputs. cso: current sense amplifier output. oos: monitor point for programmable analogue output offset voltage applied to current sense amplifiers. diag: diagnostic output. provides general fault flag output. power supplies a single power supply voltage is required. the main power sup - ply, v bb , should be connected to vbb through a reverse voltage protection circuit. a 100 nf ceramic decoupling capacitor must be connected close to the supply and ground terminals. a low power independent internal regulator provides the supply voltage, v dl , to the internal logic. a second integrated linear regulator provides the supply voltage, v io , to all logic inputs and push-pull outputs. an internal regulator provides the supply to the internal logic. all logic is guaranteed to operate correctly to below the regula - tor undervoltage levels ensuring that the a4928 will continue to operate safely until all logic is reset when a power-on-reset state is present. the a4928 will operate within specified parameters with v bb from 7 to 50 v and will function correctly with a supply down to 5.5 v . this provides a rugged solution for use in the harsh auto - motive environment. pump regulator the gate drivers are powered by a programmable voltage internal regulator which limits the supply to the drivers and therefore the maximum gate voltage. at low supply voltage, the regulated supply is maintained by a charge pump boost converter which requires a pump capacitor, typically 470 nf, connected between the cp1 and cp2 terminals. the regulated voltage, v reg , can be programmed to 8 or 11 v and is available on the vreg terminal. the voltage level is selected by the value of the vrg bit. when vrg = 1, the voltage is set to 11 v ; when vrg = 0 the voltage is set to 8 v . a suf - ficiently large storage capacitor (see application information section) must be connected to this terminal to provide the tran - sient charging current to the low-side drivers and the bootstrap capacitors. gate drives the a4928 is designed to drive external, low on-resistance, power n-channel mosfets. it will supply the large transient currents necessary to quickly charge and discharge the external mosfet gate capacitance in order to reduce dissipation in the external mosfet during switching. the charge current for the low-side drive is provided by the capacitor on the vreg termi - nal. the charge current for the high-side drives is provided by the bootstrap capacitor connected between the c and s terminals. mosfet gate charge and discharge rates may be controlled by setting a group of parameters via the serial interface or by using an external gate resistor between the gate drive output and the gate terminal of the mosfet. bootstrap supply when the high-side drivers are active, the reference voltage for the driver will rise to close to the bridge supply voltage. the supply to the driver will then have to be above the bridge supply voltage to ensure that the driver remains active. this temporary high-side supply is provided by a bootstrap capacitor connected between the bootstrap supply terminal, c, and the high-side refer - ence terminal, s. the bootstrap capacitor is independently charged to approxi - mately v reg when the associated reference s terminal is low. when the output swings high, the voltage on the bootstrap supply terminal rises with the output to provide the boosted gate voltage needed for the high-side n-channel power mosfets. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
16 bootstrap charge management the a4928 monitors the bootstrap capacitor charge voltage to ensure sufficient high-side drive. it also includes an optional bootstrap capacitor charge management system (bootstrap man - ager) to ensure that the bootstrap capacitor remains sufficiently charged under all conditions. the bootstrap manager is enabled by default but may be disabled by setting the dbm bit to 1. this may be required in systems where the output mosfet switching must only be allowed by the controlling processor. before a high-side drive can be turned on, the bootstrap capacitor voltage must be higher than the turn-on voltage threshold, v bcuv + v bcuvhys . if this is not the case, then the a4928 will attempt to charge the bootstrap capacitor by activating the low-side drive. under normal circumstances this will charge the capacitor above the turn-on voltage in a few microseconds and the high-side drive will then be enabled. the bootstrap voltage monitor remains active while the high-side drive is active and if the voltage drops below the turn-off voltage threshold, v bcuv , a charge cycle is also initiated. the bootstrap charge management circuit may actively charge the bootstrap capacitor regularly when the pwm duty cycle is very high, particularly when the pwm off-time is too short to permit the bootstrap capacitor to become sufficiently charged. in some systems, it may not be desirable to permit this feature. in this case the bootstrap manager may be disabled by setting the dbm bit to 1. if the bootstrap manager is disabled, then the user must ensure that the bootstrap capacitor does not become discharged below the bootstrap undervoltage threshold, v bcuv , or a bootstrap fault will be indicated and the outputs disabled. this can happen with very high pwm duty cycles when the charge time for the bootstrap capacitor is insufficient to ensure a sufficient recharge to match the mosfet gate charge transfer during turn on. if, for any reason, the bootstrap capacitor cannot be sufficiently charged a bootstrap fault will occursee diagnostics section for further details. top-off charge pump an additional top-off charge pump is provided, which will allow the high-side drive to maintain the gate voltage on the external mosfet indefinitely, ensuring so-called 100% pwm if required. this is a low-current trickle charge pump and is only operated after a high side has been signaled to turn on. there is a small amount of bias current drawn from the c terminal to oper - ate the floating high side circuit (<40 a) and the charge pump simply provides enough drive to ensure the bootstrap voltage, and hence the gate voltage, will not droop due to this bias current. in some applications, a safety resistor is added between the gate and source of each mosfet in the bridge. when a high-side mosfet is held in the on state, the current through the associ - ated high-side gate-source resistor (r gsh ) is provided by the high-side driver and therefore appears as a static resistive load on the top-off charge pump. the minimum value of r gsh for which the top-off charge pump can provide current, without dropping below the bootstrap undervoltage threshold, is defined in the electrical characteristics table. in all cases, the charge required for initial turn-on of the high-side gate is always supplied by the bootstrap capacitor. if the bootstrap capacitor becomes discharged, the top-off charge pump alone will not provide sufficient current to allow the mosfet to turn on. high-side gate drive a high-side gate-drive output for an external n-channel mos - fets is provided on the gh terminal. gh = 1 (or high) means that the upper-half of the driver is turned on and its drain will source current to the gate of the high-side mosfet in the exter - nal load-driving bridge, turning it on. gh = 0 (or low) means that the lower-half of the driver is turned on and its drain will sink current from the external mosfets gate circuit to the s terminal, turning it off. the reference point for the high-side drive is the load connec - tions, s. this terminal senses the voltage at the load connections. this terminal is also connected to the negative side of the boot - strap capacitor and is the negative supply reference connections for the floating high-side driver. the discharge current from the high-side mosfet gate capacitance flows through these connec - tions which should have low-impedance traces to the mosfet bridge. low-side gate drive the low-side gate-drive output on gl is referenced to the lss terminal. this output is designed to drive an external n-channel power mosfet. gl = 1 (or high) means that the upper-half of the driver is turned on and its drain will source current to the gate of the low-side mosfet in the external power bridge, turning it on. gl = 0 (or low) means that the lower-half of the driver is turned on and its drain will sink current from the external mos - fets gate circuit to the lss terminal, turning it off. the lss terminal provides the return path for discharge of the automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
17 capacitance on the low-side mosfet gate. this terminal is connected independently to the source of the low-side external mosfets through a low-impedance track. an integrated slew control feature allows the mosfet gate charge and discharge rates to be controlled via the serial interface as detailed in the gate drive control section. either the internal slew control or an external resistor between the gate drive output and the gate connection to the mosfet (as close as possible to the mosfet) can be used to control the slew rate seen at the gate, thereby controlling the di/dt and dv/dt of the voltage at the s terminal. gate drive passive pull-down each gate drive output includes a discharge circuit to ensure that any external mosfet connected to the gate drive output is held off when the power is removed. this discharge circuit appears as 950 k between the gate drive and the source connec - tions for each mosfet. it is only active when the a4928 is not driving the output to ensure that any charge accumulated on the mosfet gate has a discharge path even when the power is not connected. dead time to prevent cross-conduction (shoot through) of the power mos - fet bridge, it is necessary to have a dead-time delay between a high- or low-side turn-off and the next turn-on event. the poten - tial for cross-conduction occurs when the high-side and low-side pair of mosfets is switched at the same time, for example, at the pwm switchpoint. in the a4928, the dead time is set by the contents of the dt[9:0] bits in configuration register 0. these ten bits contain a positive integer that determines the dead time by division from the system clock. the dead time is defined as: t dead = n 50 ns where n is a positive integer defined by dt[9:0] and t dead has a minimum active value of 100 ns. for example, when dt[9:0] contains [00 0011 0000] (= 48 in decimal), then t dead = 2.4 s, typically. the accuracy of t dead is determined by the accuracy of the system clock as defined in the electrical characteristics table. the range of it is 100 ns to 51.15 s. a value of 1 or 2 in dt[9:0] will set the minimum active dead time of 100 ns. if dt[9:0] is left at the default value of zero, the dead timer is disabled and no minimum dead time is generated by the a4928. the logic that prevents permanent cross-conduction is, however, still active. adequate dead time must be generated externally by, for example, the microcontroller producing the drive signals applied to the a4928 logic inputs or control register. the internally generated dead time is only present if the on com - mand for one mosfet occurs within one dead time after the off command for the complimentary mosfet. in the case where one side of the drive is permanently off the dead time will not occur. in this case the gate drive will turn on within the specified propagation delay after the input goes high (see figure 5). gate drive control mosfet gate drives are controlled according to the values set in config 6, 7, and 8 registers. mosfet off-to-on transitions are controlled as detailed in figure 7 a. when a gate drive is commanded to turn on a current, i 1 (as defined by ir1[3:0]), is sourced on the gh or gl terminal for a duration, t 1 (defined by tr[5:0]). these parameters should typi - cally be set so as to quickly charge the mosfet input capaci - tance to the start of the miller region as drain-source voltage does not change during this period. thereafter, the current sourced on gh or gl is set to a value of i 2 (as defined by ir2[3:0]) and remains at this value while the mosfet transitions through the miller region, and reaches the fully on state. for the high-side mosfet, fully on is assumed when the drain-source voltage, v ds = v brg C v s , < v dsth . for the low-side mosfet, fully on is assumed when v ds = v s C v lss , < v dstl . i 2 should be set to achieve the required input capacitance charge time. once in the fully on state, the gh or gl output switches from current to voltage drive to hold the mosfet in the on state. if the values of ir1[3:0] and ir2[3:0] are set to 0, gh or gl produces maximum drive to turn on the mosfet as quickly as possible without attempting to control the mosfet input capaci - tance charge time ( figure 7 b). the value of tr[5:0] has no effect on switching speed. mosfet on-to-off transitions are controlled as detailed in figure 7 c. when a gate drive is commanded to turn off, a current, i 1 (as defined by if1[3:0]), is sunk by the gh or gl terminal for a duration, t1 (defined by tf[3:0]). these parameters should typically be set so as to quickly discharge the mosfet input capacitance to the start of the miller region as drain-source volt - age does not change during this period. thereafter, the current sunk by gh or gl is set to a value of i 2 (as defined by if2[3:0]) and remains at this value while the mosfet transitions through the miller region and reaches the fully off state. for the high-side mosfet, fully off is assumed when v ds (low side) = v s C v lss automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
18 < v dsth . for the low-side mosfet, fully off is assumed when v ds (high side) = v brg C v s < v dsth . i 2 should be set to achieve the required mosfet input capacitance discharge time. once in the fully off condition, the gh or gl output switches from cur - rent to voltage drive to hold the mosfet in the off state. t 1 gate drive co mmand state v ds v gs miller region i 1 off i 2 on figure 7 a: of-to-on transition (gate drive) off on gate driv e co mmand state v gs v ds miller region figure 7 b: of-to-on transition (switched) i 1 on off gate drive co mmand stat e v gs v ds i 2 t 1 miller region figure 7 c: on-to-of transition (gate drive) gate drive co mmand on off stat e v gs v ds miller region figure 7 d: on-to-of transition (switched) if the values of if1[3:0] and if2[3:0] are set to 0, gh or gl produces maximum drive to turn off the mosfet as quickly as possible without attempting to control the mosfet input capacitance discharge time ( figure 7 d). the value of tf[3:0] has no effect on switching speed. dead time, dt[9:0] in the config 0 register, must be set to a non- zero value for gate drive control to be operational. otherwise, maximum drive will be produced on all switching transitions to minimize mosfet switching times. logic control inputs two logic level digital inputs provide direct control for the gate drives, one for each drive. these are 5 v cmos threshold logic inputs and all have a typical hysteresis of 500 mv to improve noise performance. each input can be shorted to the vbb supply, up to the absolute maximum supply voltage, without damage to the input. input hs is active high and controls the high-side drive. lsn is active low and controls the low-side drive. the logical relation - ship between the inputs and the gate drive outputs is defined in table 1 . the logic sense of the inputs (active high or active low) are arranged to permit the bridge to be controlled with 1 or 2 inputs. the control inputs can be driven together to control both high- side and low-side drives with a single pwm input to provide synchronous rectification. the gate drive outputs can also be controlled through the serial interface by setting the appropriate bit in the control register. in the control register all bits are active high. the logical relation - ship between the register bit setting and the gate drive outputs is defined in table 2 . the logic inputs are combined, using logical or, with the cor - responding bits in the serial interface control register to deter - mine the state of the gate drive. the logical relationship between the combination of logic input and register bit setting and the gate drive outputs is defined in table 3 . in most applications, either the logic inputs or the serial control will be used. when using only the logic inputs to control the bridge the serial register should be left in the reset condition with all control bits set to 0. when using only the serial interface to control the bridge, the inputs should be tied such that the active-low inputs are pulled high and the active-high inputs connected to gndthat is, hs tied to gnd and lsn tied high. the internal pull-up and pull- down resistors on these inputs ensure that they go to the inactive state should they become disconnected from the control signal level. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
19 internal lockout logic ensures that the high-side output drive and low-side output drive cannot be active simultaneously. when the control inputs request active high-side and low-side at the same time, then both high-side and low side gate drives will be forced low. output disable the enable input is connected directly to the gate drive output command signal, bypassing all gate drive control logic. this can be used to provide a fast output disable (emergency cutoff). sleep mode resetn is an active-low input which allows the a4928 to enter sleep mode, in which the current consumption from the vbb sup - ply and internal logic regulator is reduced to its minimum level. when resetn is held low for longer than the reset shutdown time, t rsd , the regulator and all internal circuitry is disabled and the a4928 enters sleep mode. in sleep mode, the latched faults and corresponding fault flags are cleared. when coming out of sleep mode, the protection logic ensures that the gate drive outputs are off until the charge pump reaches its correct operating condition. the charge pump will stabilize in approximately 2 ms under nominal conditions. to allow the a4928 to start up without the need for an external logic input, the resetn terminal can be pulled to vbb with an external pull-up resistor. resetn can also be used to clear any fault conditions without entering sleep mode by taking it low for the reset pulse width, t rst . any latched short detection fault, which disables the out - puts, will be cleared, as will the serial fault register. current sense amplifier a programmable gain, differential sense amplifier is provided to allow the use of low-value sense resistors or current shunt as a low-side current sensing element. the input common mode range of the csp and csm inputs and programmable output offset allow below ground current sensing typically required for low-side current sense in pwm control of motors, or other induc - tive loads, during switching transients. the output of the sense amplifier is available at the cso output and can be used in peak or average current control systems. the output can drive up to 4.8 v to permit maximum dynamic range with higher input volt - age a-to-d converters. the gain of the sense amplifier is defined by the contents of the sag[2:0] variable as: sag gain sag gain 0 10 4 30 1 15 5 35 2 20 6 40 3 25 7 50 the output offset, v oos , of the sense amplifier is defined by the contents of the sao[3:0] variable as: sao v oos sao v oos 0 0 8 750 mv 1 0 9 1 v 2 100 mv 10 1.25 v 3 100 mv 11 1.5 v 4 200 mv 12 1.75 v 5 300 mv 13 2 v 6 400 mv 14 2.25 v 7 500 mv 15 2.5 v diagnostic monitors multiple diagnostic features provide three levels of fault monitor - ing. these include critical protection for the a4928, monitors for operational voltages and states, and detection of the power bridge and load fault conditions. all diagnostics, except for por, serial transfer error and overtemperature, can be masked by setting the appropriate bit in the mask registers. table 4 : diagnostic functions name diagnostic level por internal logic supply undervoltage causing power-on reset chip se serial transmission error chip ot chip junction overtemperature chip tw high chip junction temperature warning monitor vso vbb supply overvoltage (load dump detection) monitor vro vreg output overvoltage monitor vru vreg output undervoltage monitor oc overcurrent bridge vbs bootstrap undervoltage bridge hu high-side vgs undervoltage bridge lu low-side vgs undervoltage bridge ho high-side vds overvoltage bridge lo low-side vds overvoltage bridge automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
20 the fault status is available from the status and diagnostic regis - ters accessed through the serial interface. diag output the diag terminal provides a single diagnostic signal that outputs a general logic-level active-low fault flag. diag remains low while any fault except se or oc is present or if one of the latched faults has been detected and the outputs disabled. when the general fault flag is reset the diag output will be high. status and diagnostic registers the serial interface allows detailed diagnostic information to be read from the diagnostic registers on the sdo output terminal at any time. a system status register provides a summary of all faults in a single read transaction. the status register is always output on sdo when any register is written. the first bit (bit 15) of the status register contains a common fault flag, ff, which will be high if any of the fault bits in the status register have been set. this allows fault condition to be detected using the serial interface by simply taking strn low. as soon as strn goes low the first bit in the status register can be read on sdo to determine if a fault has been detected at any time since the last fault register reset. in all cases the fault bits in the diagnostic registers are latched and only cleared after a fault register reset. ff provides an indication that a fault has occurred since the last fault reset and one or more fault bits have been set. note that ff (bit 15) does not provide the same function as the general fault flag output on the diag terminal. the fault flag output on the diag terminal provides an indication that either a fault is present or the outputs have been disabled due to a latched fault state. ff provides an indication that a fault has occurred since the last fault reset and one or more fault bits have been set. chip-level protection chip-wide parameters critical for correct operation of the a4928 are monitored. these include maximum chip temperature, minimum internal logic supply voltage and the serial interface transmission. these three monitors are necessary to ensure that the a4928 is able to respond as specified. chip fault state: internal logic undervolt - age (por) the a4928 has an independent internal logic regulator to supply the internal logic. this is to ensure that external events, other than loss of supply, do not prevent the a4928 from operating correctly. the internal logic supply regulator will continue to operate with a low supply voltage, for example, if the main supply voltage drops to a very low value during a severe cold crank event. in extreme low supply circumstances, or during power-up or power-down, an undervoltage detector ensures that the a4928 operates correctly. the logic supply undervoltage lockout cannot be masked as it is essential to guarantee correct operation over the full supply range. when power is first applied to the a4928, the internal logic is prevented from operating, and all gate drive outputs held in the off state until the internal regulator voltage, v dl , exceeds the logic supply undervoltage lockout rising (turn-on) threshold, v dlon . at this point, all serial control registers will be reset to their power-on state and all fault states will be reset. the ff bit and the por bit in the status register will be set to one to indicate that a power-on-reset has taken place. the a4928 then goes into its fully operational state and begins operating as specified. once the a4928 is operational, the internal logic supply continues to be monitored. if, during the operational state, v dl drops below logic supply undervoltage lockout falling (turn-off) threshold, v dloff , then the logical function of the a4928 cannot be guar - anteed and the outputs will be immediately disabled. the a4928 will enter a power-down state and all internal activity, other than the logic regulator voltage monitor will be suspended. if the logic supply undervoltage is a transient event, then the a4928 will fol - low the power-up sequence above as the voltage rises. chip fault state: overtemperature (ot) if the chip temperature rises above the overtemperature threshold, t jf , the overtemperature bit, ot, will be set in the status register. if esf = 1 when an overtemperature is detected, all gate drive outputs will be disabled automatically. if esf = 0, then no circuitry will be disabled and action must be taken by the user to limit the power dissipation in some way so as to prevent overtemperature damage to the chip and unpredictable device operation. when the temperature drops below t jf by more than the hysteresis value, t jfhys , the fault state is cleared, and when esf = 1, the outputs are re-enabled. the overtemperature bit remains in the status register until reset. chip fault state: serial error (se) if there are more than 16 rising edges on sck or if strn goes high and there are fewer than 16 rising edges on sck or the parity is not odd, then the write will be cancelled without writing data to the registers and the se bit will be set to indicate a data transfer error. if the transfer is a write, then the status register will not be reset. if the transfer is a diagnostic register read, then the addressed register will not be reset. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
21 operational monitors parameters related to the safe operation of the a4928 in a system are monitored. these include parameters associated with external active and passive components, power supplies, and interaction with external controllers. voltages relating to driving the external power mosfets are monitored, specifically v reg , the bootstrap capacitor voltage, and the v gs of each gate drive output. the main supply voltage, v bb , is only monitored for overvoltage events. it is not monitored for minimum voltage since the critical minimum voltage is generated by the vreg charge pump regulator provided by the a4928. monitor: vreg voltage (vr: vro, vru) the internal charge-pump regulator supplies the low-side gate driver and the bootstrap charge current. it is critical to ensure that the regulated voltage, v reg , at the vreg terminal is sufficiently high before enabling any of the outputs. if v reg goes below the vreg undervoltage threshold, v roff , the vreg undervoltage bit, vru, will be set in the diagnostic register. all gate drive outputs will go low, the motor drive will be disabled, and the motor will coast. when v reg rises above the rising threshold, v ruon , the gate drive outputs are re-enabled and the fault state is cleared. the vru bit remains in the diagnostic register until cleared. the vreg undervoltage monitor circuit is active during power up and all gate drives will be low until v reg is greater than approximately 8 v (with vrg = 1). note that this is sufficient to turn on standard threshold external power mosfets at a battery voltage as low as 5.5 v , but the on-resistance of the mosfet may be higher than its specified maximum. the vreg undervoltage monitor can be disabled by setting the vru bit in the mask register. although not recommended, this can allow the a4928 to operate below its minimum specified sup - ply voltage level with a severely impaired gate drive. the speci - fied electrical parameters will not be valid in this condition. the output of the vreg regulator is also monitored to detect any overvoltage applied to the vreg terminal. if v reg goes above the vreg overvoltage threshold, v rov , the vreg overvoltage bit, vro, will be set in the diagnostic register. no action will be taken as the gate drive outputs are protected from overvolt - age by independent zener clamps. when v reg falls below v rov by more than the hysteresis voltage, v rovhys , the fault state is cleared but vro bit remains in the diagnostic register until cleared. monitor: temperature warning (tw) if the chip temperature rises above the temperature warning threshold, t jw , the hot warning bit, tw, will be set in the status register. no action will be taken by the a4928. when the temper - ature drops below t jw by more than the hysteresis value, t jwhys , the fault state is cleared and the tw bit remains in the status register until reset. monitor: vbb supply overvoltage (vso) if v bb rises above the vbb overvoltage warning threshold, v bbov , then the vso bit will be set in the diagnostic 2 register and the vs bit will be set in the status register. the general fault flag will be set but all gate drive outputs will continue to func - tion. when v bb drops below the falling vbb overvoltage warn - ing threshold, v bbov C v bbovhys , the general fault flag will be cleared but the vso and vs bits will remain set. the fault state will only be reset by a low pulse on the resetn input, by a serial read of the diagnostic or status register or by a power-on reset. power bridge and load faults bridge: overcurrent detect (oc) the output from the sense amplifier can be compared to an over - current threshold voltage, v oct , to provide indication of overcur - rent events. v oct , is generated by a 4-bit dac with a resolution of 300 mv and defined by the contents of the oc[3:0] variable and the contents of the sao[3:0] variable. v oct is approximately defined as: v oct = [(n + 1) 300 mv] where n is a positive integer defined by oct[3:0] any offset programmed on sao[3:0] is applied to both the cur - rent sense amplifier output, v cso , and the overcurrent threshold, v oct , and has no effect on the overcurrent threshold, i oct . the relationship between the threshold voltage and the threshold cur - rent is approximately defined as: i oct = v oct / (r s a v ) where v oct is the overcurrent threshold voltage programmed by oct[3:0], r s lvwkhvhqvhuhvlvwrudohlqdqg v is the sense amp gain defined by sag[2:0]. the output from the overcurrent comparator is filtered by an overcurrent qualifier circuit. this circuit uses a timer to verify that the output from the comparator is indicating a valid over - current event. the qualifier can operate in one of two ways, debounce or blanking, selected by the ocq bit. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
22 in the default debounce mode, a timer is started each time the comparator output indicates an overcurrent. this timer is reset when the comparator changes back to indicate normal operation. if the debounce timer reaches the end of the timeout period, set by t ocq , then the overcurrent event is considered valid and the overcurrent bit, oc, will be set in the diag 2 register. in the optional blanking mode, a timer is started when a low- side gate drive is turned on. the output from the comparator is ignored (blanked) for the duration of the timeout period, set by t ocq . if a comparator output indicates an overcurrent event when the blanking timer is not active then the overcurrent event is considered valid and the overcurrent bit, oc, will be set in the diag 2 register. when a valid overcurrent is detected, no action is taken and only the oc bit is set. the fault state will be reset by a low pulse on the resetn input, by a serial read of the diagnostic or status register or by a power-on reset. bridge: bootstrap capacitor undervoltage fault (vbs) the a4928 monitors the bootstrap capacitor charge voltage to ensure sufficient high-side drive. it also includes an optional bootstrap capacitor charge management system (bootstrap man - ager) to ensure that the bootstrap capacitor remains sufficiently charged under all conditions. the bootstrap manager is enabled by default but may be disabled by setting the dbm bit to 1. this may be required in systems where the output mosfet switching must only be allowed by the controlling processor. if the bootstrap manager is disabled, then the user must ensure that the bootstrap capacitor does not become discharged below the bootstrap undervoltage threshold, v bcuv , or a bootstrap fault will be indicated and the outputs disabled. this can happen with very high pwm duty cycles when the charge time for the boot - strap capacitor is insufficient to ensure a sufficient recharge to match the mosfet gate charge transfer during turn on. when the bootstrap manager is active, the bootstrap capacitor voltage must be higher than the turn-on voltage limit before a high-side drive can be turned on. if this is not the case, then the a4928 will attempt to charge the bootstrap capacitor by activat - ing the low-side drive. under normal circumstances, this will charge the capacitor above the turn-on voltage in a few microsec - onds and the high-side drive will then be enabled. the boot - strap voltage monitor remains active while the high-side drive is active, and if the voltage drops below the turn-off voltage, a charge cycle is also initiated. if there is a fault that prevents the bootstrap capacitor charg - ing during the managed recharge cycle, then the charge cycle will timeout after typically 200 s and the bootstrap undervolt - age fault is considered to be valid. if the bootstrap manager is disabled and a bootstrap undervoltage is detected when a high- side mosfet is active or being switched on, then the bootstrap undervoltage is immediately valid. the action taken when a valid bootstrap undervoltage fault is detected and the fault reset conditions depend on the state of the esf bit. if esf = 0, the fault state will be latched, the bootstrap under - voltage fault bit in the status register, v bs , will be set, and the high-side mosfet will be disabled. the fault state, but not the bootstrap undervoltage fault bit, will be reset by a low pulse on the resetn input or the next time the mosfet is commanded to switch on. if the mosfet is being driven with a pwm signal, then this will usually mean that the mosfet will be turned on again each pwm cycle. if this is the case, and the fault condition remains, then a valid fault will again be detected after the timeout period and the sequence will repeat. the fault state will be reset by a low pulse on the resetn input, by a serial read of the diag - nostic or status register or by a power-on reset. if esf = 1, the fault will be latched, the associated bootstrap undervoltage fault bit will be set, and all mosfets will be dis - abled. the fault state will be reset by a low pulse on the resetn input, by a serial read of the diagnostic or status register or by a power-on reset. the bootstrap undervoltage monitor can be disabled by setting the vbs bit in the mask register. although not recommended, this can allow the a4928 to operate below its minimum speci - fied supply voltage level with a severely impaired gate drive. the specified electrical parameters may not be valid in this condition. bridge: mosfet vds overvoltage fault (dso: ho, lo) faults on the external mosfets are determined by monitoring the drain-source voltage of the mosfet and comparing it to a drain-source overvoltage threshold, v dst . v dst is generated by an internal dac and is defined by the values in the vt[5:0] vari - able. this variable provides the input to a 6-bit dac with a least significant bit value of typically 50 mv. the output of the dac produces the threshold voltage approximately defined as: v dst = n 50 mv where n is a positive integer defined by vt[5:0] automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
23 the drain-source voltage for the low-side mosfet is measured between the s terminal and the lss terminal. using the lss terminal rather than the ground connection avoids adding any low-side current sense voltage to the real low-side drain-source voltage and avoids false vds fault detection. the drain-source voltage for the high-side mosfet is measured between the s terminal and the vbrg terminal. using the vbrg terminal rather than vbb avoids adding any reverse diode volt - age or high-side current sense voltage to the real high-side drain- source voltage and avoids false vds fault detection. the vbrg terminal is an independent low-current sense input to the top of the mosfet bridge. it should be connected indepen - dently and directly to the common connection point for the drain of the power bridge mosfet at the positive supply connection point in the bridge. the input current to the vbrg terminal is proportional to the drain-source threshold voltage, v dst , and is approximately: i vbrg = 72 v dst + 52 where i vbrg is the current into the vbrg terminal in a and v dst is the drain-source threshold voltage described above. note that the vbrg terminal can withstand a negative voltage up to C5 v . this allows the terminal to remain connected directly to the top of the power bridge during reverse battery conditions where the body diodes of the power mosfets are used to clamp the negative voltage. the output from each vds overvoltage comparator is filtered by a vds fault qualifier circuit. this circuit uses a timer to verify that the output from the comparator is indicating a valid vds fault. the duration of the vds fault qualifying timer, t vdq , is determined by the contents of the tvd[9:0] variable. t vdq is approximately defined as: t vdq = n 100 ns where n is a positive integer defined by tvd[9:0]. the qualifier can operate in one of two ways: debounce mode or blanking mode, selected by the vdq bit. in the default debounce mode, a timer is started each time the comparator output indicates a vds fault detection when the corresponding mosfet is active. this timer is reset when the comparator changes back to indicate normal operation. if the debounce timer reaches the end of the timeout period set by t vdq , then the vds fault is considered valid and the corresponding vds fault bit, lo or ho, will be set in the diagnostic register. in the optional blanking mode, a timer is started when a gate drive is turned on. the output from the vds overvoltage com - parator for the mosfet being switched on is ignored (blanked) for the duration of the timeout period, set by t vdq . if the com - parator output indicates an overvoltage event when the mosfet is switched on and the blanking timer is not active then the vds fault is considered valid and the corresponding vds fault bit, lo or ho will be set in the diagnostic register. if a valid vds fault is detected, the fault will be latched and the associated mosfet will be disabled. this state will remain until reset depending on the value set in the esf bit. if esf = 1, the fault state will only be reset by a low pulse on the resetn input, by a serial read of the diagnostic register, or by a power-on reset. if esf = 0, the fault state, but not the vds fault bit, will be reset the next time the mosfet is commanded to switch on. if the mosfet is being driven with a pwm signal, then this will usu - ally mean that the mosfet will be turned on again each pwm cycle. if this is the case, and the fault conditions remains, then a valid fault will again be detected after the timeout period and the sequence will repeat. the fault state will be reset by a low pulse on the resetn input, by a serial read of the diagnostic register, or by a power-on reset. if esf = 0, care must be taken to avoid damage to the mosfet where the vds fault is detected. although the mosfet will be switched off as soon as the fault is detected at the end of the fault validation timeout, it is possible that it could still be damaged by excessive power dissipation and heating. to limit any damage to the external mosfets or the load, the mosfet should be fully disabled by logic inputs from the external controller. bridge: vgs undervoltage (gsu: hu, lu) to ensure that the gate drive output is operating correctly, each gate drive output voltage is independently monitored, when active, to ensure the drive voltage, v gs , is sufficient to fully enhance the power mosfet in the external bridge. if v gs , on any active gate drive output, goes below the gate drive undervoltage warning, v gsuv , the general fault flag will be active and the corresponding gate drive undervoltage bit, hu or lu, will be set in the diagnostic register. no other action will be taken. when v gs rises above v gsuv by more than the hysteresis voltage, v gsuvhys , the general fault flags go inactive. the fault bits remain in the diagnostic register until cleared. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
24 for high-side vgs comparator, the v gsuv threshold is set 1 v(typ) below the voltage on the c terminal, and for the low-side gate comparator, the v gsuv threshold is set 1 v(typ) below v reg . the output from each vgs undervoltage comparator is filtered by a vgs fault qualifier circuit. this circuit uses a timer to verify that the output from the comparator is indicating a valid vgs fault. the duration of the vgs fault qualifying timer, t vdq , is determined by the contents of the tvd[9:0] variable. t vdq is approximately defined as: t vdq = n 100 ns where n is a positive integer defined by tvd[9:0] the qualifier can operate in one of two ways: debounce mode or blanking mode, selected by the vdq bit. in debounce mode (the default setting), a timer is started each time the comparator output indicates a vgs fault detection when the corresponding mosfet is active. this timer is reset when the comparator changes back to indicate vgs is within 1 v of the volt - age on the c terminal (high-side gate drive) or v reg (low-side gate drive). if the debounce timer reaches the end of the timeout period set by t vdq , then the vgs fault is considered valid. in blanking mode (optional), a timer is started when any gate drive is turned on or turned off. the outputs from the vgs undervolt - age comparators for all mosfets are ignored (blanked) for the duration of the timers active period set by t vdq . if any gate drive changes state while a blanking period is in progress, the timer is re-triggered, resulting in an extended overall blanking time. if any comparator output indicates a vgs fault and the blanking timer is not active, then the vgs fault is considered valid. the vdq and tvd[9:0] qualifier parameters apply to both the vgs undervoltage and vds overvoltage monitors. mosfet fault state: short to supply a short from the load connections to the battery or vbb connec - tion is detected by monitoring the voltage across the low-side mosfet using the s terminal and the lss terminal. this drain- source voltage is then compared to the low-side drain-source threshold voltage, v dstl . if the blanking timer is active, the output from the vds overvoltage comparator will be ignored for t vdq . while the low-side vds fault is detected, the vds fault bit, lo, will be set in the diagnostic register and the low-side mosfet will be disabled. when esf is set to 1, both mosfets will be disabled. mosfet fault state: short to ground a short from the load connection to ground is detected by monitoring the voltage across the low-side mosfet using the s terminal and the voltage at vbrg. this drain-source voltage is then compared to the high-side drain-source threshold volt - age, v dsth . if the blanking timer is active, the output from the vds overvoltage comparator will be ignored for t vdq . while the low-side vds fault is detected, the vds fault bit, ho, will be set in the diagnostic register and the high-side mosfet will be disabled. when esf is set to 1, both mosfets will be disabled. fault action the action taken when one of the diagnostic functions indicates a fault is listed in table 5 . when a fault is detected, a corresponding fault state is consid - ered to exist. in some cases, the fault state only exists during the time the fault is detected. in other cases, when the fault is only detected for a short time, the fault state is latched (stored) until reset. the faults that are latched are indicated in table 5 . latched fault states are always reset when resetn is taken low, a power- on-reset state is present or when the associated fault bit is read through the serial interface. any fault bits that have been set in the status or diagnostic register are only reset when a power- on-reset state is present or when the associated fault bit is read through the serial interface. resetn low will not reset the fault bits in the status or diagnostic registers. the fault conditions power-on-reset and vreg undervoltage are considered critical to the safe operation of the a4928 and the system. if these faults are detected, then the gate drive outputs are automatically driven low and both mosfets in the bridge held in the off state. this state will remain until the fault is removed. for the overtemperature fault conditions, the action taken depends on the status of the esf bit. if a fault is detected on any of these two diagnostics and esf = 1, then all the gate drive outputs will be driven low and all mosfets in the bridge held in the off state. this state will remain until the fault is removed. if esf = 0, then the gate drive outputs will not be affected. if a vds fault or bootstrap undervoltage fault is detected, then the action taken will also depend on the status of the esf bit, but these faults are handled as a special case. if a fault is detected on any of these two diagnostics and esf = 1, then both gate drive outputs will be driven low and both mosfets in the bridge will be held in the off state. when esf = 1, this fault state will be latched and remain until reset. if a vds fault or bootstrap undervoltage fault automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
25 is detected and esf = 0, then only the gate drive output to the mosfet where the fault was detected will be driven low and the mosfet will be held in the off state. when esf = 0, the vds fault or bootstrap undervoltage fault state will be latched but will be reset the next time the mosfet is commanded to switch on. for all other faults, the gate drive outputs will remain enabled. fault masks individual diagnosticsexcept power-on reset, serial transmis - sion error, and overtemperaturecan be disabled by setting the corresponding bit in the mask register. power-on-reset cannot be disabled because the diagnostics and the output control depend on the logic regulator to operate correctly. if a bit is set to one in the mask register, then the corresponding diagnostic will be completely disabled. no fault states for the disabled diagnostic will be generated and no fault flags or diagnostic bits will be set. see mask register definition for bit allocation. care must be taken when diagnostics are disabled to avoid potentially damag - ing conditions. table 5 : fault actions fault description disable outputs fault state latched esf = 0 esf = 1 no fault no no C power-on-reset yes [1] yes [1] no vreg undervoltage yes [1] yes [1] no vreg overvoltage no no no vbb overvoltage no no no overtemperature no yes [1] no temperature warning no no no serial transmission error no no no bootstrap undervoltage yes [2] yes [1] yes overcurrent no no no vds overvoltage yes [2] yes [1] yes vgs undervoltage no no no [1] both gate drives low, both mosfets off. [2] gate drive to the affected mosfet low, only the affected mosfet off. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
26 table 6 : serial register definition* 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0: config 0 0 0 0 0 wr dt9 dt8 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 p 1 1 1 1 1 1 1 1 1 1 1: config 1 0 0 0 1 wr oct3 oct2 oct1 oct0 vt5 vt4 vt3 vt2 vt1 vt0 p 1 0 0 1 0 1 1 0 0 0 2: config 2 0 0 1 0 wr ocq vdq p 0 0 0 0 0 0 0 0 0 0 3: config 3 0 0 1 1 wr tvd9 tvd8 tvd7 tvd6 tvd5 tvd4 tvd3 tvd2 tvd1 tvd0 p 1 1 1 1 1 1 1 1 1 1 4: config 4 0 1 0 0 wr vrg p 0 0 0 1 0 0 0 0 0 0 5: config 5 0 1 0 1 wr sao3 sao2 sao1 sao0 sag2 sag1 sag0 p 0 0 1 1 1 1 0 1 0 1 6: config 6 0 1 1 0 wr tr5 tr4 tr3 tr2 tr1 tr0 tf3 tf2 tf1 tf0 p 0 0 0 0 0 1 0 0 0 1 7: config 7 0 1 1 1 wr ir13 ir12 ir11 ir10 if13 if12 if11 if10 p 0 0 0 0 0 0 0 0 0 0 8: config 8 1 0 0 0 wr ir23 ir22 ir21 ir20 if23 if22 if21 if20 p 0 0 0 0 0 0 0 0 0 0 9: not used 1 0 0 1 wr p 0 0 0 0 0 0 0 0 0 0 10: mask 0 1 0 1 0 wr vbs tw hu lu p 0 0 0 0 0 0 0 0 0 0 11: mask 1 1 0 1 1 wr vro vru vso ho lo p 0 0 0 0 0 0 0 0 0 0 12: diag 0 1 1 0 0 0 hu lu p 0 0 0 0 0 0 0 0 0 0 13: diag 1 1 1 0 1 0 vro vru ho lo p 0 0 0 0 0 0 0 0 0 0 14: diag 2 1 1 1 0 0 vso vbs oc p 0 0 0 0 0 0 0 0 0 0 *power-on reset value shown below each input register bit. continued on the next page... serial interface automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
27 table 6 :serial register definition (continued) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15: control 1 1 1 1 wr dbm esf hsr lsr p 0 0 0 1 0 0 0 0 0 0 status ff por se ot tw vs vr oc vbs gsu dso p 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 *power-on reset value shown below each input register bit. a three-wire synchronous serial interface, compatible with spi, is used to control the features of the a4928. the sdo terminal can be used, during a serial transfer, to provide diagnostic feedback and readback of the register contents. the a4928 can be operated without the serial interface using the default settings and the logic control inputs; however, application specific configurations are only possible by setting the appropri - ate register bits through the serial interface. in addition to setting the configuration bits, the serial interface can also be used to control the bridge mosfets directly. the serial interface timing requirements are specified in the electrical characteristics table, and illustrated in figure 4. data is received on the sdi terminal and clocked through a shift register on the rising edge of the clock signal input on the sck terminal. strn is normally held high, and is only brought low to initiate a serial transfer. no data is clocked through the shift register when strn is high, allowing multiple slave units to use common sdi and sck connections. each slave then requires an independent strn connection. the sdo output assumes a high-impedance state when strn is high, allowing a common data readback con - nection. when 16 data bits have been clocked into the shift register, strn must be taken high to latch the data into the selected register. when this occurs, the internal control circuits act on the new data and the registers are reset depending on the type of transfer. if there are more than 16 rising edges on sck or if strn goes high and there are fewer than 16 rising edges on sckeither being described as a framing errorthe write will be cancelled without latching data to the register. the status register will not be reset. the first four bits, d[15:12], in a serial word, are the register address bits giving the possibility of 16 register addresses. the fifth bit, wr (d[11]), is the write/read bit. when wr is 1, the following 10 bits, d[10:1], clocked in from the sdi terminal, are written to the addressed register. when wr is 0, then no data is written to the serial registers and the contents of the addressed register are clocked out on the sdo terminal. the last bit in any serial transfer, d[0], is a parity bit (p) that is set to ensure odd parity in the complete 16-bit word. odd parity means that the total number of 1s in any transfer should always be an odd number. this ensures that there is always at least one bit set to 1 and one bit set to 0 and allows detection of stuck-at faults on the serial input and output data connections. the parity bit is not stored but generated on each transfer. in addition to the addressable registers, a read-only status register is output on sdo for all register addresses when wr is set to 1. for all serial transfers, the five bits output on sdo will always be the first five bits from the status register. register data is output on the sdo terminal msb first while strn is low and changes to the next bit on each falling edge of sck. the first bit, which is always the ff bit from the status register, is output as soon as strn goes low. registers 12, 13, and 14 contain diagnostic fault indicators and are read only. if the wr bit for these registers is set to 1, then the data input through sdi is ignored and the contents of the status register is clocked out on the sdo terminal then reset as for a normal write. no other action is taken. if the wr bit for these registers is set to 0, then the data input through sdi is ignored and the contents of the addressed register is clocked out on the sdo terminal and the addressed register is reset. if a framing or parity error is detected, the se bit is set in the status register to indicate a data transfer error. this fault condi - tion can be cleared by a subsequent valid serial write or by a power-on-reset. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
28 configuration registers nine registers are used to configure the operating parameters of the a4928. config 0: bridge timing settings: ? dt[9:0], a 10-bit integer to set the dead time, t dead , in 50 ns increments. config 1: bridge monitor setting: ? oct[3:0], a 4-bit integer to set the overcurrent threshold volt - age, v oct , in 300 mv increments. ? vt[5:0], a 6-bit integer to set the drain-source threshold volt - age, v dst , in 50 mv increments. config 2: bridge monitor setting: ? ocq, selects the overcurrent qualifier mode, blank or debounce. ? vdq, selects the vds and vgs qualifier mode, blank or debounce. config 3: bridge monitor setting: ? tvd[9:0], a 10-bit integer to set the vds and vgs fault veri - fication time, t vdq , in 100 ns increments. config 4: regulator configuration: ? vrg, selects the regulator and gate drive voltage. config 5: sense amplifier setting: ? sao[3:0], a 4-bit integer to set the sense amplifier offset up between 0 and 2.5 v . ? sag[2:0], a 3-bit integer to set the sense amplifier gain between 10 and 50 v/v . config 6: gate drive time setting: ? tr[5:0], a 6-bit integer to set the high-side and low-side i 1 time in 50 ns increments. ? tf[3:0], a 4-bit integer to set the high-side and low-side i 1 time in 50 ns increments. config 7: gate drive current setting: ? ir1[3:0] , a 4-bit integer to set the mosfet turn-on i 1 current in 4.5 ma increments. ? if1[3:0] , a 4-bit integer to set the mosfet turn-off i 1 current in 5.3 ma increments. config 8: gate drive current setting: ? ir2[3:0] , a 4-bit integer to set the mosfet turn-on i 2 current in 4.5 ma increments. ? if2[3:0] , a 4-bit integer to set the mosfet turn-off i 2 current in 5.3 ma increments. diagnostic registers in addition to the read-only status register, five registers provide detailed diagnostic management and reporting. two mask register allow individual diagnostics to be disabled and three read-only diagnostic registers provide fault bits for individual diagnostic tests and monitors. if a bit is set to one in the mask register, then the cor - responding diagnostic will be completely disabled. no fault states for the disabled diagnostic will be generated and no fault flags or diagnostic bits will be set. these bits in the diagnostic registers are reset on completion of a successful read of the register. mask 0: individual bits to disable bootstrap (vbs), temperature warning (tw), and the vgs undervoltage diagnostic monitors (hu and lu). mask 1: individual bits to disable the voltage regulator (vro, vru and vso) and the vds overvoltage diagnostic monitors (ho and lo). diagnostic 0 (read only): individual bits indicating faults detected in vgs diagnostic moni - tors (hu and lu). diagnostic 1 (read only): individual bits indicating faults detected in voltage regulator (vro and vru) and vds overvoltage diagnostic monitors (ho and lo). diagnostic 2 (read only): individual bits indicating faults detected in the vbb supply volt - age and overcurrent (vbs and oc). control register the control register contains one control bit for each mosfet and some system function settings: ? dbm, disabled bootstrap management function. ? esf, defines the action taken when a short is detected. see diagnostics section for details of fault actions. ? hsr and lsr, mosfet control bits. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
29 status register there is one status register in addition to the 16 addressable registers. when any register transfer takes place, the first five bits output on sdo are always the most significant five bits of the status register regardless of whether the addressed register is being read or written (see serial timing diagram). the content of the remaining eleven bits will depend on the state of the wr bit input on sdi. when wr is 1, the addressed register will be written and the remaining eleven bits output on sdo will be the least significant ten bits of the status register followed by a parity bit. when wr is 0, the addressed register will be read and the remaining eleven bits will be the contents of the addressed register followed by a parity bit. the read-only status register provides a summary of the chip sta - tus by indicating if any diagnostic monitors have detected a fault. the most significant three bits of the status register (ff, por, and se) indicate critical system faults. bits ot and tw provide indicators for specific individual monitors and the remaining bits are derived from the contents of the three diagnostic registers. the contents and mapping to the diagnostic registers are listed in table 7 . table 7 : status register mapping status register bit diagnostic related diagnostic register bits ff status flag none por power-on-reset none se serial error none ot overtemperature none tw temperature warning none vs vbb monitor vso vr vreg monitor vru, vro oc overcurrent oc vbs bootstrap uv vbs gsu vgs uv hu, lu dso vds ov ho, lo uv = undervoltage, ov = overvoltage the read-only status register provides a summary of the chip status by indicating if any diagnostic monitors have detected a fault. the most significant three bits of the status register (ff, por, and se) indicate critical system faults. bits ot and tw provide indicators for specific individual monitors and the remaining bits are derived from the contents of the three diagnos - tic registers. the contents and mapping to the diagnostic registers is listed in table 7 . the first most significant bit in the register is the diagnostic status flag, ff. this is high if any bits in the status register are set. when strn goes low to start a serial write, the sdo outputs the diagnostic status flag. this allows the main controller to poll the a4928 through the serial interface to determine if a fault has been detected. if no faults have been detected, then the serial transfer may be terminated without generating a serial read fault by ensur - ing that sck remains high while strn is low. when strn goes high, the transfer will be terminated and sdo will go into its high- impedance state. the second most significant bit is the por bit. at power-up or after a power-on-reset, the ff bit and the por bit are set, indi - cating to the external controller that a power-on-reset has taken place. all other diagnostic bits are reset and all other registers are returned to their default state. note that a power-on-reset only occurs when the output of the internal logic regulator rises above its undervoltage threshold. power-on-reset is not affected by the state of the vbb supply or the vreg regulator output. in general, the vr and vru bits will also be set following a power-on-reset as the regulators will not have reached their respective rising undervoltage thresholds until after the register reset is completed. the third bit in the status register is the se bit, which indicates that the previous serial transfer was not completed successfully. bits ot and tw are the fault bits for the two temperature moni - tors. if one or more of these faults are no longer present, then the corresponding fault bits will be reset following a successful read of the status register. resetting only affects latched fault bits for faults that are no longer present. for any static faults that are still present, for example overtemperature, the fault flag will remain set after the reset. the remaining bits, vs, vr, oc, vbs, gsu, and dso are all derived from the contents of the diagnostic registers. vs, oc, and vbs are reset either by directly reading the status register or when the corresponding contents of the diagnostic register are read and reset. vr, gsu, and dso are only cleared when the cor - responding contents of the diagnostic register are read; they can - not be reset by reading the status register. a fault indicated on any of the related diagnostic register bits will set the corresponding status bit to 1. in the case of vr, gsu, and dso faults, the related diagnostic register must be read to determine the exact fault and clear the fault state if the fault condition has cleared. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
30 serial register reference 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0: config 0 0 0 0 0 wr dt9 dt8 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 p 1 1 1 1 1 1 1 1 1 1 1: config 1 0 0 0 1 wr oct3 oct2 oct1 oct0 vt5 vt4 vt3 vt2 vt1 vt0 p 1 0 0 1 0 1 1 0 0 0 2: config 2 0 0 1 0 wr ocq vdq p 0 0 0 0 0 0 0 0 0 0 3: config 3 0 0 1 1 wr tvd9 tvd8 tvd7 tvd6 tvd5 tvd4 tvd3 tvd2 tvd1 tvd0 p 1 1 1 1 1 1 1 1 1 1 4: config 4 0 1 0 0 wr vrg p 0 0 0 1 0 0 0 0 0 0 config 0 dt[9:0] dead time. t dead = n 50 ns where n is a positive integer defined by dt[9:0], e.g. for the power-on-reset condition. dt[9:0] = [11 1111 1111] then t dead = 51.15 s. the range of t dead is 100 ns to 51.15 s. selecting a value of 1 or 2 will set the dead time to 100 ns. a value of zero disables the dead time. config 1 vt[5:0] vds overvoltage threshold. v dst = n 50 mv where n is a positive integer defined by vt[5:0], e.g. for the power-on-reset condition. vt[5:0] = [01 1000] then v dst = 1.2 v . the range of v dst is 0 to 3.15 v . config 2 vdq vds and vgs fault qualifier mode. vdq vds fault qualifier default 0 debounce d 1 blank config 3 tvd[9:0] vds and vgs verification time. t vdq = n 100 ns where n is a positive integer defined by tvd[9:0], e.g. for the power-on-reset condition. tvd[9:0] = [11 1111 1111] then t vdq = 102.3 s. the range of t vdq is 0 to 102.3 s. config 4 vrg v reg voltage level. vrg vreg voltage default 0 8 v 1 11 v d oct[3:0] overcurrent threshold. v oct = (n + 1) 300 mv where n is a positive integer defined by oct[3:0] e.g. for the power-on-reset condition. oct[3:0] = [1001] then v oct = 3 v . the range of v oct is 0.3 to 4.8 v . ocq overcurrent time qualifier mode. ocq qualifier default 0 debounce d 1 blank automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
31 serial register reference (continued) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5:config 5 0 1 0 1 wr sao3 sao2 sao1 sao0 sag2 sag1 sag0 p 0 0 1 1 1 1 0 1 0 1 config 2 sao[3:0] sense amp offset. where sao is a positive integer defined by sao[3:0]. sao offset default 0 0 mv 1 0 mv 2 100 mv 3 100 mv 4 200 mv 5 300 mv 6 400 mv 7 500 mv 8 750 mv 9 1.0 v 10 1.25 v 11 1.5 v 12 1.75 v 13 2.0 v 14 2.25 v 15 2.5 v d sag[2:0] sense amp offset. where sag is a positive integer defined by sag[2:0]. sag gain default 0 10 1 15 2 20 3 25 4 30 5 35 d 6 40 7 50 automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
32 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6: config 6 0 1 1 0 wr tr5 tr4 tr3 tr2 tr1 tr0 tf3 tf2 tf1 tf0 p 0 0 0 0 0 1 0 0 0 1 7: config 7 0 1 1 1 wr ir13 ir12 ir11 ir10 if13 if12 if11 if10 p 0 0 0 0 0 0 0 0 0 0 8: config 8 1 0 0 0 wr ir23 ir22 ir21 ir20 if23 if22 if21 if20 p 0 0 0 0 0 0 0 0 0 0 serial register reference (continued) config 6 tr[5:0] mosfet turn-on t 1 time. t 1 = (n + 1) 50 ns where n is a positive integer defined by tr[3:0], e.g. if tr[5:0] = [00 0001] then t 1 = 100 ns. the range of t 1 is 50 to 3200 ns. tf[3:0] mosfet turn-off t 1 time. t 1 = (n + 1) 50 ns where n is a positive integer defined by tf[3:0], e.g. for the power-on-reset condition. tf[3:0] = [0001] then t 1 = 100 ns. the range of t 1 is 50 to 800 ns. config 7 ir1[3:0] mosfet turn-on i 1 current. i 1 = n C4.5 ma where n is a positive integer defined by ir1[3:0], e.g. if ir1[3:0] = [1000] then i 1 = C36 ma the range of i1 is C4.5 ma to C67.5 ma. selecting a value of 0 will set maximum gate drive to turn on the mosfet as quickly as possible. if1[3:0] mosfet turn-off i 1 current. i 1 = n 5.3 ma where n is a positive integer defined by if1[3:0], e.g. if if1[3:0] = [1000] then i 1 = 42.4 ma. the range of i 1 is 5.3 to 79.5 ma. selecting a value of 0 will set maximum gate drive to turn on the mosfet as quickly as possible. config 8 ir2[3:0] mosfet turn-on i 2 current. i 2 = n C4.5 ma where n is a positive integer defined by ir2[3:0], e.g. if ir2[3:0] = [1000] then i 2 = C36 ma. the range of i 2 is C4.5 to C67.5 ma. selecting a value of 0 will set maximum gate drive to turn on the mosfet as quickly as possible. if2[3:0] mosfet turn-off i 2 current. i 2 = n 5.3 ma where n is a positive integer defined by if2[3:0], e.g. if if2[3:0] = [1000] then i 2 = 42.4 ma. the range of i 2 is 5.3 to 79.5 ma. selecting a value of 0 will set maximum gate drive to turn on the mosfet as quickly as possible. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
33 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 10: mask 0 1 0 1 0 wr vbs tw hu lu p 0 0 0 0 0 0 0 0 0 0 11: mask 1 1 0 1 1 wr vro vru vso ho lo p 0 0 0 0 0 0 0 0 0 0 serial register reference (continued) mask 0 vbs bootstrap undervoltage tw temperature warning hu high-side vgs undervoltage lu low-side vgs undervoltage xxx fault mask default 0 fault detection permitted d 1 fault detection disabled mask 1 vro vreg overvoltage vru vreg undervoltage vso vbb overvoltage ho high-side vds overvoltage lo low-side vds overvoltage automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
34 serial register reference (continued) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 12: diag 0 1 1 0 0 0 hu lu p 0 0 0 0 0 0 0 0 0 0 13: diag 1 1 1 0 1 0 vro vru ho lo p 0 0 0 0 0 0 0 0 0 0 14: diag 2 1 1 1 0 0 vso vbs oc p 0 0 0 0 0 0 0 0 0 0 status ff por se ot tw vs vr oc vbs gsu dso p 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 diag 0 (read only) hu high-side vgs undervoltage lu low-side vgs undervoltage diag 1 (read only) vro vreg overvoltage vru vreg undervoltage ho high-side vds overvoltage lo low-side vds overvoltage diag 2 (read only) vso vbb overvoltage vbs bootstrap undervoltage oc overcurrent on sense amp xxx status 0 no fault detected 1 fault detected status (read only) ff diagnostic register flag por power-on-reset se serial error ot overtemperature tw high temperature warning vs vbb fault vr vreg out of range oc overcurrent vbs bootstrap undervoltage gsu vgs undervoltage dso vds overvoltage xxx status 0 no fault detected 1 fault detected status register bit mapping status register bit related diagnostic register bits ff none por none se none ot none tw none vs vso vr vru, vro oc oc vbs vbs gsu hu, lu dso ho, lo u = undervoltage, o = overvoltage automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
35 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15: control 1 1 1 1 wr dbm esf hsr lsr p 0 0 0 1 0 0 0 0 0 0 serial register reference (continued) control dbm dbm bootstrap manager default 0 active d 1 disabled esf enable stop on fail. esf recirculation default 0 no stop on fail. report fault. 1 stop on fail. report fault. d hsr high-side gate drive lsr low-side gate drive see table 2 and table 3 for control logic operation. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
36 dead-time selection the choice of power mosfet and external series gate resistance determines the selection of the dead time. the dead time, t dead , should be made long enough to ensure that one mosfet has stopped conducting before the complementary mosfet starts conducting. this should also account for the tolerance and varia - tion of the mosfet gate capacitance, the series gate resistance and the on-resistance of the driver in the a4928. t dead v t 0 v gha - v s a v gl a v gs l v gs h figure 8 : minimum dead time figure 8 shows the typical switching characteristics of a pair of complementary mosfets. ideally, one mosfet should start to turn on just after the other has completely turned off. the point at which a mosfet starts to conduct is the threshold voltage v t0 . the dead time should be long enough to ensure that the gate- source voltage of the mosfet that is switching off is just below v t0 before the gate-source voltage of the mosfet that is switch - ing on rises to v t0 . this will be the minimum theoretical dead time, but in practice the dead time will have to be longer than this to accommodate variations in mosfet and driver parameters for process variations and overtemperature. bootstrap capacitor selection the a4928 requires a bootstrap capacitor c. to simplify this description of the bootstrap capacitor selection criteria, generic naming is used here. so, for example, c boot , q boot , and v boot refer to the bootstrap capacitor, and q gate refers to any of the two associated mosfets. c boot must be correctly selected to ensure proper operation of the devicetoo large and time will be wasted charging the capacitor, resulting in a limit on the maxi - mum duty cycle and pwm frequency; too small and there can be a large voltage drop at the time the charge is transferred from c boot to the mosfet gate. to keep the voltage drop due to charge sharing small, the charge in the bootstrap capacitor, q boot , should be much larger than q gate , the charge required by the gate: q boot >> q gate a factor of 20 is a reasonable value, so q boot = c boot v boot = q gate 20 or = q gate 20 c boot v boot where v boot is the voltage across the bootstrap capacitor. 7khrowdjhgurs9dfurvvwkherrwvwudsfdsdflwrudvwkh026 - fet is being turned on, can be approximated by: = c boot q gate ?v vrirudidfwruri9zlooehri9 boot . the maximum voltage across the bootstrap capacitor under normal operating conditions is v reg (max). however in some circumstances the voltage may transiently reach a maximum of 18 v , which is the clamp voltage of the zener diode between the c terminal and the s terminal. in most applications with a good ceramic capacitor, the working voltage can be limited to 16 v . bootstrap charging it is good practice to ensure the high-side bootstrap capacitor is completely charged before a high-side pwm cycle is requested. the time required to charge the capacitor, t charge , in s, is approximated by: = 100 c boot ?v t charge where c boot lvwkhdohriwkherrwvwudsfdsdflwrulqq)dqg9 is the required voltage of the bootstrap capacitor. at power up and when the drivers have been disabled for a long time, the bootstrap fdsdflwrufdqehfrpsohwhoglvfkdujhg,qwklvfdvh9fdqeh considered to be the full high-side drive voltage, 12 v . otherwise, 9lvwkhdprqwrirowdjhgursshggulqjwkhfkdujhwudqvihu which should be 400 mv or less. the capacitor is charged when - ever the s terminal is pulled low and current flows from the capaci - tor connected to the vreg terminal through the internal bootstrap diode circuit to c boot . application information automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
37 vreg capacitor selection the internal reference, v reg , supplies current for the low-side gate-drive circuits and the charging current for the bootstrap capacitors. when a low-side mosfet is turned on, the gate- drive circuit will provide the high transient current to the gate that is necessary to turn the mosfet on quickly. this current, which can be several hundred milliamperes, cannot be provided directly by the limited output of the vreg regulator but must be supplied by an external capacitor, c reg , connected between the vreg terminal and gnd the turn-on current for the high-side mosfet is similar in value but is mainly supplied by the bootstrap capacitor. however, the bootstrap capacitor must then be recharged from c reg through the vreg terminal. unfortunately, the bootstrap recharge can occur a very short time after the low-side turn on occurs. this means that the value of c reg between vreg and gnd should be high enough to minimize the transient voltage drop on vreg for the combination of a low-side mosfet turn on and a bootstrap capacitor recharge. for block commutation control (trapezoidal drive), where only one high side and one low side are switching during each pwm period, a minimum value of 20 c boot is reasonable. for sinusoidal control schemes, a minimum value of 40 c boot is recommended. as the maximum work - ing voltage of c reg will never exceed v reg , the parts voltage rating can be as low as 15 v. however, it is recommended that a capacitor rated to at least twice the maximum working volt - age should be used to reduce any impact operating voltage may have on capacitance value. for best performance, c reg should be ceramic rather than electrolytic. c reg should be mounted as close to the vreg terminal as possible. current sense amplifier configuration amplifier gain, a v , and output offset zero point voltage, v oos , may be set to a range of values by the sag[2:0] and sao[3:0] variables respectively as defined in the current sense ampli - fiers section above. it is important that both values are selected to ensure the absolute voltage at the cso output, v cso , remains within the amplifiers dynamic range, v csout , and the dynamic range of any downstream signal processing circuitry. allowance must be made for both positive and negative current flows within the sense resistor. with reference to figure 3, the relationship between phase cur - rent i ph , sense resistor value, r s , and differential amplifier input voltage, v id is given by: v id = v csp C v csm = i ph r s the current sense amplifiers output voltage on csxo with respect to the programmed value of output offset on oos is: v csd = (v csp C v csm ) a v the absolute voltage on csxo with respect to ground is there - fore: v cso = [(v csp C v csm ) a v ] + v oos if, for example, the following parameter values are assumed: ? r s = 1 m ? i ph = C20a to +40a ? a v = 20 (sag[2:0] = 0b010) ? v oos = 1 v (sao[3:0] = 0b1001) v id ranges between C20 mv and +40 mv and v cso between 0.6 v and 1.8 v. v cso remains within the amplifier dynamic range, v csout , of 0.3 v to 4.8 v . however, if a v is increased to 50, v cso attempts to drive to 0 v and 3.0 v , the amplifier dynamic range limits are not complied with, and the amplifier output saturates at its negative limit. this situation could be rem - edied by reducing a v to 30 (0.4 v < v cso < 2.2 v) or increasing v oos to 1.5 v (0.5 v < v cso < 3.5 v). current sense amplifier output signals as defined in figure 3, the current sense amplifier output signals on the cso pins are internally referenced to the voltage on the oos pin. consequently, the signal voltages on cso should be measured differentially with respect to oos (v csd ). alterna - tively, the voltages on both cso (v cso ) and oos (v oos ) may be measured consecutively with respect to ground and the values subtracted to give the required output signal voltages as v csd = v cso C v oos . the input offset voltage, v ios , and the associated drift, v ios , multiplied by the selected amplifier gain, a v , represent the offset and offset drift limits that apply to v cs d. the output offset error, e vo , and output offset drift, v oosd , limits apply directly to v oos . e vo and v oosd do not affect current sense output accuracy. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
38 input/output structures c 16 v g h s g l l ss 16 v 16 v v reg 56 v sd i sc k 2 k k k k k k k k vb rg 56 v vbb 56 v dl 6 v cp1 20 v cp2 vreg 16 v 6 v 6 v 7.5 v figure 9 a: gate drive outputs figure 9b: supplies figure 9c: sdi, sck inputs figure 9d: strn inputs figure 9e: resetn, enable, hs inputs figure 9f: sdo output figure 9g: diag output figure 9 i: csm, csp inputs figure 9j: cso, oos outputs figure 9h: lsn input automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
39 layout recommendations careful consideration must be given to pcb layout when design - ing high-frequency, fast-switching, high-current circuits: ? the exposed thermal pad should be connected to the gnd terminal. ? minimize stray inductance by using short, wide copper tracks at the drain and source terminals of all power mosfets. this includes load lead connections, the input power bus.this will minimize voltages induced by fast switching of large load currents. ? consider the addition of small (100 nf) ceramic decoupling capacitor across the source and drain of the power mosfets to limit fast transient voltage spikes caused by track inductance. ? keep the gate discharge return connections s and lss as short as possible. any inductance on these tracks will cause negative transitions on the corresponding a4928 terminals, which may exceed the absolute maximum ratings. if this is likely, consider the use of clamping diodes to limit the negative excursion on these terminals with respect to the gnd terminal. ? supply decoupling, typically a 100 nf ceramic capacitor, should be connected between vbb and gnd as close to the a4928 terminals as possible. ? supply decoupling should be connected between vreg and gnd as close to the a4928 terminals as possible. ? check the peak voltage excursion of the transients on the lss terminals with reference to the gnd terminal using a close-grounded (tip & barrel) probe. if the voltage at any lss terminal exceeds the absolute maximum in the datasheet, add additional clamping and/or capacitance between the lss terminal and the gnd terminal. ? gate charge drive paths and gate discharge return paths may carry a large transient current pulse. therefore, the traces from gh, gl, s, and lss should be as short as possible to reduce the trace inductance . ? provide an independent connection between the lss terminal to the source of the low-side mosfet in the power bridge. connection of the lss terminal directly to the gnd terminal is not recommended as this may inject noise into sensitive functions such as the various voltage monitors. ? a low-cost diode can be placed in the connection to vbb to provide reverse battery protection. in reverse battery conditions, it is possible to use the body diodes of the power mosfets to clamp the reverse voltage to approximately 4 v . in this case, the additional diode in the vbb connection will prevent damage to the a4928 and the vbrg input will survive the reverse voltage. figure 10: supply routing suggestions s upp ly c o mm on + s upp ly load pad s gh gl lss vbb vreg c on troller supply g round power g r ound a4928 vb rg gnd optional reverse batt ery protection r s automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
40 package outline drawing figure 11 : package lp, 24-lead tssop with exposed pad for reference only ?n ot for tooling use (reference mo-153 adt) nott o scale dimensions in millimeters dimensions exclusive of mold ?ash, gate burrs, and dambar protrusions exact case and lead con?guration at supplier discretion within limits shown a 1.20 max 0.15 0.00 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 24x 0.65 bsc 0.25 bsc 21 24 7.80 0.10 4.400.10 6.400.20 gauge plane seating plane a b b exposed thermal pad (bottom surface); dimensions may vary with device 4.32 nom 3 nom 0.65 6.10 3.00 4.32 1.65 0.45 c c pcb layout reference view terminal #1 mark area reference land pattern layout (reference ipc7351 tsop65p640x120-25m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com
41 for the latest version of this document, visit our website: www.allegromicro.com revision history number date description C january 4, 2018 initial release 1 january 31, 2019 minor editorial updates copyright ?2019, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. copies of this document are considered uncontrolled documents. automotive half-bridge mosfet driver a4928 allegro microsystems, llc 955 perimeter road manchester, nh 03103-3353 u.s.a. www.allegromicro.com

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